In the field of digital signal processing, the need for interfacing a low clock rate component with a high clock rate component is very common. For example, in a digital still camera, real-time data from a charge-coupled device (CCD) is transferred to a high speed memory, such as a synchronous dynamic random access memory (SDRAM). For these purposes, “real-time” means that data is transferred at a rate fast enough to avoid a perceivable delay in operation of the system, in this example, a digital still camera. The CCD operates at a clock rate of about 12 MHz, while the SDRAM operates at a clock rate of about 54 MHz. To smooth the transfer of the real-time data flow, an interface between the low clock rate CCD and the high clock rate SDRAM is needed to accommodate the difference between the clock rates.
There are two primary prior art approaches for the interface of two components having different operating speeds: a First-In-First-out (FIFO) buffering configuration and a dual-port memory buffering configuration.
A diagram of a prior art FIFO configuration is shown in FIG. 1. FIFO comprises a memory 2 that is accessible by the data source 4 anytime there is space available and is accessible by the destination 6 anytime there is data available from the source. FIFO also comprises hardware control logic 8, such as a read/write access pointer controller, to control the access to the FIFO by both the data source and the destination so as to ensure that the data will be transferred correctly. In the case that the clock rate of the data source is higher than that of the destination, the control logic must detect when the memory of the FIFO is full and send a signal to the data source, if the memory is detected as full, to hold the data transmitted from the source until the memory is detected as nearly empty. In the other case when the clock rate of the destination is higher than that of the data source, the control logic must detect when the memory of the FIFO is empty or nearly empty and send a signal to the destination, if the memory is detected as empty or nearly empty, to hold the access to the FIFO by the destination until the memory is detected as full. This operation requires relatively complex control logic and a relatively long timing delay, which slows down the performance of the component with the higher clock rate. Such a solution is practical only if using a slow clock source.
Dual-port memory circuits (i.e. a memory array accessible by two ports) are a more versatile form of time domain boundary buffer. The read and write operations of a dual-port buffer are based on address rather than write order, thereby allowing the reading of data in a different order than it was written in, for example. Lock-outs are used in a dual-port buffer to prevent reading from a memory element while it is being written. Dual-port buffers can be arranged to not slow down the performance of the component with the higher clock rate if the read/write operations are coordinated properly. Unfortunately, the implementation of a dual-port buffer is more complicated than that of a FIFO and is difficult to integrate into an integrated circuit die. Hence, a dual port memory is typically used as a discrete component, adding to system size and complexity. In addition, the manufacturing costs of dual-port buffers are comparatively higher than single-port memory circuits.
There is therefore a need in the industry for a cost-effective interface solution that allows real-time data transfer between two components having different clock rates.